#25 🚀 Are you calculating the dead time of your modulation correctly?
The Newsletter of High Frequency folks
👋 Hello! Dr. Molina here! 👨🔧
Yesterday we talk about the concept of ZVS. I have studied this concept for several converters, however, the most interesting are the Bridges topologies, because there are a lot of possibilities without adding extra components.
As we saw yesterday, the key parameters for having ZVS are:
the Dead Time between switches in the same leg,
the parasitic capacitance of the switch (+ the transformer),
and the series inductance of the transformer (Leakage or external inductance)
Today I will focus on the calculation of the dead time. Most engineers are calculating not calculating the dead time. They focus on experimenting.
I always recommend measuring the parasitics and then, making the calculations.
You need to measure the magnetizing inductance, the parasitic capacitance of the primary, and the leakage inductance of the transformer.
Do you know how to measure properly the leakage inductance?- We have to talk about this in another post…
You have to find the parasitic capacitance of your switch at the voltage you are going to work at in the datasheet. In the picture below you can see the typical curves of voltage against Capacitance (or energy).
With this information, we can calculate the range of ZVS with the relation between the energy stored in the parasitics and this equation. When the energy stored in the Llk is higher than the stored in the capacitance of the switch, you have ZVS.
And the Dead Time?
The dead time is the interval when all these effects happen. This speed depends on the instantaneous current of the transformer as it is shown in the equation below [1].
DT is the dead time, Ip is the peak instantaneous current, Coss is the switch parasitic capacitance and Ctrafo is the parasitic capacitance of the primary. As you can see, when Ip decrease, you will need more DT.
In my opinion, the optimal point is determined by the losses in the semiconductors. At light losses, there are fewer conduction losses, you can assume some switching losses, but be careful with the dV/dt (that’s for another post).
By the way, today we are offering Training where you can use our online simulator for one month, you can calculate very accurately the Leakage inductance of your transformer and avoid 80% of the hardware iterations. Besides, receive great lessons on magnetic design and the possibility of technical consultancy during the whole month.
Here is the link:
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Sincerely,
Chema 👋
Reference:
[1] J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee and B. H. Cho, "Design considerations for high-voltage high-power full-bridge zero-voltage-switched PWM converter," Fifth Annual Proceedings on Applied Power Electronics Conference and Exposition, 1990, pp. 275-284, doi: 10.1109/APEC.1990.66420.